RegViz: Visualize GTDNSR Bitfield

Renesas Electronics /R7FA2A1AB /GPT320 /GTDNSR

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Interpret as GTDNSR

DSCARBH=0, DSGTRGAR=0, DSGTRGAF=0, DSELCA=0, DSELCC=0, DSCBFAL=0, DSCAFBL=0, DSCARBL=0, DSCBRAL=0, DSCBFAH=0, DSCBRAH=0, DSELCD=0, DSGTRGBR=0, DSCAFBH=0, DSELCB=0, DSGTRGBF=0

Description

General PWM Timer Down Count Source Select Register

Fields

DSGTRGAR	GTETRGA Pin Rising Input Source Counter Count Down Enable 0 (0): Counter count down is disable at the rising edge of GTETRGA input 1 (1): Counter count down is enable at the rising edge of GTETRGA input
DSGTRGAF	GTETRGA Pin Falling Input Source Counter Count Down Enable 0 (0): Counter count down is disable at the falling edge of GTETRGA input 1 (1): Counter count down is enable at the falling edge of GTETRGA input
DSGTRGBR	GTETRGB Pin Rising Input Source Counter Count Down Enable 0 (0): Counter count down is disable at the rising edge of GTETRGB input 1 (1): Counter count down is enable at the rising edge of GTETRGB input
DSGTRGBF	GTETRGB Pin Falling Input Source Counter Count Down Enable 0 (0): Counter count down is disable at the falling edge of GTETRGB input 1 (1): Counter count down is enable at the falling edge of GTETRGB input
DSCARBL	GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable 0 (0): Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 0 1 (1): Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 0
DSCARBH	GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable 0 (0): Counter count down is disable at the rising edge of GTIOCA input when GTIOCB input is 1 1 (1): Counter count down is enable at the rising edge of GTIOCA input when GTIOCB input is 1
DSCAFBL	GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable 0 (0): Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 0 1 (1): Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 0
DSCAFBH	GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable 0 (0): Counter count down is disable at the falling edge of GTIOCA input when GTIOCB input is 1 1 (1): Counter count down is enable at the falling edge of GTIOCA input when GTIOCB input is 1
DSCBRAL	GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable 0 (0): Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 0 1 (1): Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 0
DSCBRAH	GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable 0 (0): Counter count down is disable at the rising edge of GTIOCB input when GTIOCA input is 1 1 (1): Counter count down is enable at the rising edge of GTIOCB input when GTIOCA input is 1
DSCBFAL	GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable 0 (0): Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 0 1 (1): Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 0
DSCBFAH	GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable 0 (0): Counter count down is disable at the falling edge of GTIOCB input when GTIOCA input is 1 1 (1): Counter count down is enable at the falling edge of GTIOCB input when GTIOCA input is 1
DSELCA	ELC_GPTA Event Source Counter Count Down Enable 0 (0): Counter count down is disable at the ELC_GPTA input 1 (1): Counter count down is enable at the ELC_GPTA input
DSELCB	ELC_GPTB Event Source Counter Count Down Enable 0 (0): Counter count down is disable at the ELC_GPTB input 1 (1): Counter count down is enable at the ELC_GPTB input
DSELCC	ELC_GPTC Event Source Counter Count Down Enable 0 (0): Counter count down is disable at the ELC_GPTC input 1 (1): Counter count down is enable at the ELC_GPTC input
DSELCD	ELC_GPTD Event Source Counter Count Down Enable 0 (0): Counter count down is disable at the ELC_GPTD input 1 (1): Counter count down is enable at the ELC_GPTD input

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